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MC10EP57 4:1 Differential Multiplexer
The MC10EP57 is a fully differential 4:1 multiplexer. By leaving the SEL1 line open (pulled LOW via the input pulldown resistors) the device can also be used as a differential 2:1 multiplexer with SEL0 input selecting between D0 and D1. The fully differential architecture of the EP57 makes it ideal for use in low skew applications such as clock distribution. The SEL1 is the most significant select line. The binary number applied to the select inputs will select the same numbered data input (i.e., 00 selects D0). Multiple VBB outputs are provided for single-ended or AC coupled interfaces. In these scenarios, the VBB output should be connected to the data bar inputs and bypassed via a 0.01F capacitor to ground. Note that the VBB output can source/sink up to 0.5mA of current without upsetting the voltage level. All VCC and VEE pins must be externally connected to power supply to guarantee proper operation
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TSSOP-20 DT SUFFIX CASE 948E
MARKING DIAGRAM
* * * * * * * * * * * * * *
350ps Typical Propagation Delays Typical Frequency 3.0GHz 20-Lead TSSOP Package PECL mode: 3.0V to 5.5V VCC with VEE = 0V ECL mode: 0V VCC with VEE = -3.0V to -5.5V Internal Input Resistors: Pulldown on D, D Q Output will default LOW with inputs open or at VEE ESD Protection: >2KV HBM, >100V MM VBB Outputs New Differential Input Common Mode Range Moisture Sensitivity Level 1, Indefinite Time Out of Drypack. For Additional Information, See Application Note AND8003/D Useful as Either 4:1 or 2:1 Multiplexer Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34 Transistor Count = 584 devices
VCC 20 SEL1 SEL0 19 18 VCC 17 Q 16 Q 15 VCC VBB1 VBB2 14 13 12 VEE 11
MC10 EP57 ALYW
A L Y W
= Assembly Location = Wafer Lot = Year = Work Week
*For additional information, see Application Note AND8002/D
PIN DESCRIPTION
PIN D0-3, D0-3 SEL0, 1 VBB1, VBB2 Q, Q VCC VEE FUNCTION ECL Diff. Data Inputs ECL Mux Select Inputs ECL Reference Output Voltage ECL Data Outputs Positive Supply Negative, 0 Supply
FUNCTION TABLE SEL1 L L H H SEL0 L H L H DATA OUT D0, D0 D1, D1 D2, D2 D3, D3
4:1
ORDERING INFORMATION
Device 1 VCC 2 D0 3 D0 4 D1 5 D1 6 D2 7 D2 8 D3 9 D3 10 VEE MC10EP57DT MC10EP57DTR2 Package TSSOP TSSOP Shipping 75 Units/Rail 2500 Tape & Reel
Figure 1. 20-Lead TSSOP (Top View) and Logic Diagram
(c) Semiconductor Components Industries, LLC, 2000
1
April, 2000 - Rev. 2
Publication Order Number: MC10EP57/D
MC10EP57
MAXIMUM RATINGS*
Symbol VEE VCC VI VI Iout IBB TA Tstg JA JC Tsol Power Supply (VCC = 0V) Power Supply (VEE = 0V) Input Voltage (VCC = 0V, VI not more negative than VEE) Input Voltage (VEE = 0V, VI not more positive than VCC) Output Current VBB Sink/Source Current{ Operating Temperature Range Storage Temperature Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Solder Temperature (<2 to 3 Seconds: 245C desired) Still Air 500lfpm Continuous Surge Parameter Value -6.0 to 0 6.0 to 0 -6.0 to 0 6.0 to 0 50 100 0.5 -40 to +85 -65 to +150 140 100 23 to 41 5% 265 Unit VDC VDC VDC VDC mA mA C C C/W C/W C
* Maximum Ratings are those values beyond which damage to the device may occur. { Use for inputs of same package only.
DC CHARACTERISTICS, ECL/LVECL (VCC = 0V; VEE = -5.5V to -3.0V) (Note 4.)
-40C Symbol IEE VOH VOL VIH VIL VBB Characteristic Power Supply Current (Note 1.) Output HIGH Voltage (Note 2.) Output LOW Voltage (Note 2.) Input HIGH Voltage Single Ended Input LOW Voltage Single Ended Output Voltage Reference Min 40 -1135 -1995 -1210 -1935 -1550 -1450 Typ 52 -1060 -1810 Max 65 -885 -1685 -885 -1610 -1350 0.0 150 SEL, D D 0.5 -150 0.5 -150 Min 40 -1070 -1995 -1145 -1870 -1500 -1400 25C Typ 52 -945 -1745 Max 65 -820 -1620 -820 -1545 -1300 0.0 150 0.5 -150 Min 40 -1010 -1995 -1085 -1810 -1450 -1350 85C Typ 52 -885 -1685 Max 65 -760 -1560 -760 -1485 -1250 0.0 150 Unit mA mV mV mV mV mV V A A
VIHCMR Input HIGH Voltage Common Mode Range (Note 3.) IIH IIL Input HIGH Current Input LOW Current
VEE+2.0
VEE+2.0
VEE+2.0
NOTE: 10EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained. 1. VCC = 0V, VEE = VEEmin to VEEmax, all other pins floating. 2. All loading with 50 ohms to VCC-2.0 volts. 3. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. 4. Input and output parameters vary 1:1 with VCC.
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MC10EP57
DC CHARACTERISTICS, LVPECL (VCC = 3.3V 0.3V, VEE = 0V) (Note 8.)
-40C Symbol IEE VOH VOL VIH VIL VBB Characteristic Power Supply Current (Note 5.) Output HIGH Voltage (Note 6.) Output LOW Voltage (Note 6.) Input HIGH Voltage Single Ended Input LOW Voltage Single Ended Output Voltage Reference Min 40 2165 1305 2090 1365 1750 2.0 1850 Typ 52 2240 1490 Max 65 2415 1615 2415 1690 1950 3.3 150 SEL, D D 0.5 -150 0.5 -150 Min 40 2230 1305 2155 1430 1800 2.0 1900 25C Typ 52 2355 1555 Max 65 2480 1680 2480 1755 2000 3.3 150 0.5 -150 Min 40 2290 1305 2215 1490 1850 2.0 1950 85C Typ 52 2415 1615 Max 65 2540 1740 2540 1815 2050 3.3 150 Unit mA mV mV mV mV mV V A A
VIHCMR Input HIGH Voltage Common Mode Range (Note 7.) IIH IIL Input HIGH Current Input LOW Current
NOTE: 10EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained. 5. VCC = 3.3V, VEE = 0V, all other pins floating. 6. All loading with 50 ohms to VCC-2.0 volts. 7. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. 8. Input and output parameters vary 1:1 with VCC.
DC CHARACTERISTICS, PECL (VCC = 5.0V 0.5V, VEE = 0V) (Note 12.)
-40C Symbol IEE VOH VOL VIH VIL VBB Characteristic Power Supply Current (Note 9.) Output HIGH Voltage (Note 10.) Output LOW Voltage (Note 10.) Input HIGH Voltage Single Ended Input LOW Voltage Single Ended Output Voltage Reference Min 40 3865 3005 3790 3065 3450 2.0 3550 Typ 52 3940 3190 Max 65 4115 3315 4115 3390 3650 5.0 150 SEL, D D 0.5 -150 0.5 -150 Min 40 3930 3005 3855 3130 3500 2.0 3600 25C Typ 52 4055 3255 Max 65 4180 3380 4180 3455 3700 5.0 150 0.5 -150 Min 40 3990 3005 3915 3190 3550 2.0 3650 85C Typ 52 4115 3315 Max 65 4240 3440 4240 3515 3750 5.0 150 Unit mA mV mV mV mV mV V A A
VIHCMR Input HIGH Voltage Common Mode Range (Note 11.) IIH IIL Input HIGH Current Input LOW Current
NOTE: 10EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained. 9. VCC = 5.0V, VEE = 0V, all other pins floating. 10. All loading with 50 ohms to VCC-2.0 volts. 11. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. 12. Input and output parameters vary 1:1 with VCC.
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MC10EP57
AC CHARACTERISTICS (VCC = 0V; VEE = -3.0V to -5.5V) or (VCC = 3.0V to 5.5V; VEE = 0V)
-40C Symbol fmax tPLH, tPHL tSKEW tJITTER VPP tr, tf Characteristic Maximum Toggle Frequency (Note 13.) Propagation Delay to Output Differential D->Q, Q COM_SEL, SEL->Q, Q Within-Device Skew (Note 14.) Duty Cycle Skew (Note 15.) Cycle-to-Cycle Jitter Input Voltage Swing (Diff.) Output Rise/Fall Times (20% - 80%) Q, Q 150 70 TBD 800 120 1200 170 150 70 250 300 350 400 450 500 100 TBD 800 140 1200 200 150 70 275 320 Min Typ Max Min 25C Typ 3.0 Max Min 85C Typ Max Unit GHz ps 375 420 475 520 100 TBD 800 150 1200 220 320 320 420 450 520 575 100 ps ps mV ps
13. Fmax guaranteed for functionality only. 14. Within-Device Skew is defined as identical transitions on similar paths through a device. 15. Skew is measured between outputs under identical transitions. Duty cycle skew is defined only for differential operation when the delays are measured from the cross point of the inputs to the cross point of the outputs.
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MC10EP57
PACKAGE DIMENSIONS
TSSOP-20 DT SUFFIX 20 PIN PLASTIC TSSOP PACKAGE CASE 948E-02 ISSUE A
20X
K REF
M
0.15 (0.006) T U
S
0.10 (0.004)
TU
S
V
S
K K1 J J1
B L
PIN 1 IDENT 1 10
-U-
SECTION N-N 0.25 (0.010)
N 0.15 (0.006) T U
S
A -V- N F
C D 0.100 (0.004) -T- SEATING
PLANE
G
H
DETAIL E
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III III III
M DETAIL E
2X
L/2
20
11
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
-W-
DIM A B C D F G H J J1 K K1 L M
MC10EP57
Notes
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MC10EP57
Notes
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MC10EP57
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MC10EP57/D

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